The evolution in usage of a staggeringly large number of gates is leading the user community to demand a new design methodology. The next step in a natural progression that began with the CAD (layout) tools of the 1970s, was followed by the CAE (schematic entry + simulation) era of the 1980s, and evolved into the RTL (synthesis + simulation/formal analysis) age of the 1990s. Throughout those decades, designers created circuits and systems from a few hundred gates made of discrete parts or functions selected from a catalog to a few thousand gates engraved in gate-arrays, to hundreds of thousands gates etched in ASICs.
Some will remember the false starts in-between: the silicon compilers, mega-cells, bit slices, ECL variations. However, the EDA industry fused compiler and hardware-description language technologies into a revolutionary RTL Synthesis methodology that turned RTL-based designs into gate-level designs that remain the standard today. Almost all semiconductor companies have adopted these methodologies for chip design.
The next logical step is from RTL to high-level design by way of the emerging standard design
approach of architectural synthesis, which enables designers to specify input and output
requirements and let the tool determine the details as it automatically implements the RTL code.
In 2000, Lauro joined Get2Chip as Product Marketing Director. Before that, Lauro held a senior marketing positions at Synopsys, Mentor Graphics and Teradyne. He also worked at Olivetti and Siemens as system designer. He has published several articles in trade magazines, presented at EDA conferences, and has taught publicly.
Lauro holds a doctorate in Electronic Engineering from the Universita` degli Studi di Trieste, Italy.