EXPERTISE SUMMARY:

• High-tech patent analysis, assertion case prep, claim vs product attribute charts, prior art searches, reverse engineering, market analysis, IP valuation, inventor interviews, negotiation support, multi-project support
• Recent patent projects: IC I/O drivers, PC User Interface, MEMS, IC Fab processes, CDMA/GSM wireless, telecomm
• M&A pre-investment due diligence of IP
• Commercialization of University research
• IC device physics, fabrication processes
• Non-Volatile memory, MRAM, Flash
• Cu interconnects, Low K dielectrics, CMP Photolithography, layer deposition, etching
• Audit IC & MEMS fabrication facilities, processes, & reliability issue prevention
• Assessment of technology capability, risks
• NSF Grant Peer reviewer  SBIR semi mfg
• Author, Speaker on Nanotechnology topics

PROFESSIONAL SUMMARY:

• Over 20 years experience in the semiconducor Industry with broad exposure to electronics.
• Innovated & implemented leading edge integraed circuit fabrication technologies for multiple generations, spanning a 20 year time period.
• 4 years experience in patent analysis, assertion support, valuation, related Reverse Engineering. Drafted Applications.
• Active for over 2 years identifying and assessing University graduate research commercialization.
• Ongoing consultations on patents and semiconductor fabrication for the Round Table Group (RTG) and the Gerson Lehrman Group. Member Silicon Valley Expert Witness Group (SVEIWG)
• Directed development of fabrication processes for semiconductor devices and ICs in the context of Non-volatile memory, A/D converters, CMOS logic, BiCMOS telecomm, SOC, embedded Flash
• Assessed IC fabrication technology maturity at factories in Japan, Taiwan, Europe, Singapore, Malaysia & the US, for capability & readiness for high volume manufacture.
• Judge of annual UC Berkeley / Stanford / UCSF Nanotech Graduate research poster papers