Twenty years experience with logic design, verifcation and synthesis of digital ASICs.

• Verification of digital IC designs using SystemVerilog, Verisity Specman "e" language, Vera, C and C++ programming languages, an scripting tools: PERL, TCL, shell scripting and make files.
• Logic Design and Synthesis
• Trainings for design engineers for language and applications of Hardware Design Languages and methodology.

EDA Tools:

• SystemVerilog with OVM Class libraries and SVA Assertions
• Vera with RVM Class libraries
• Verilog, VHDL and Synopsys' DC Shell
• FPGA Toolsets from Xilinx and Altera
• C and C++
• scripting tools: PERL, TCL, Pythonk Java, shell scripting, make files