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Digital Signal Processing: Software, programmable logic. Signal Processing: Joint time-frequency.
Charles Hanes  Member Hanes Consulting
Windows Device Driver Development, especially for 1394 & Digital Video. C/C++, Perl, Java, HTML, XML, MPEG, RS485, Atmel AVR, GCC
David L. Hecht  Member DLH Consulting
Digital imaging, scanning, printing, watermarking, document security, optics, lasers, ultrasonics. Analog/mixed signal/RFIC design, power management, signal conditioning Audio, video, multimedia and signal processing. Expert witness.
Andy Hospodor, Ph.D.  Member Gridplan, Inc.
Data storage, distributed systems, Grid computing, performance analysis, simulation and modeling. Business development, research, chip architecture, performance analysis, patents. Project Management, Instrument Design, Documentation Services High-Speed Digital Circuits: Design and Modeling.

Consultant Details

211 Stockbridge Ave.
Atherton, CA 94027
650.368.0831
650.796.5156 (cell)
m.hooper@ieee.org

Analog, Mixed Signal, RFIC Design

  • Analog/mixed signal/RFIC design
  • Power management
  • Signal conditioning
  • University teaching

He earned the B.S.E.E./U.C. Davis (1989), M.S.E.E./SJSU (1994) and the Ph.D.E.C.E./Georgia Institute of Technology (2005). His master's and doctoral theses focused on analog IC design.

He has been responsible for the management and/or design of various semiconductor projects at the system level, transistor level and device level in CMOS and Bipolar technologies. Some of the projects included: (a) leading the design and research for CMOS signal conditioning circuitry to interface with Xicor's EEPOT technology;(b) leading the design and research of a joint project between ON Semiconductor and Georgia Tech for a high frequency CMOS DC-DC converter (PWM architecture); (c) setting up, implementing and managing a small mixed signal IC design center at Gerogia Tech for ON Semiconductor associated with project (b); (d) managing and developing the power management circuitry for programming analog floating-gate circuits in a standard submicron CMOS process; (e) leading the device design, mask design, process design, testing and fabrication of a BJT with a narrow base width;(f) preparing customer CMOS databases for the mask shop; (g) teaching a graduate level class in analog IC design and (h) and collaborating with various semiconductor organizations for the development of a CMOS architecture to interface with a MEMS device. In another project although smaller in scope, he conducted research concerning phase noise in VCOs. Many of the design projects comprised the phases from concept to production: research, design, simulation, layout, schematic and design rule verification, tapeout, testing, characterizing and helping to support customer applications.

Dr. Hooper has been employed at: National Semiconductor, Xicor, Georgia Tech, Unitech Research Inc., SJSU, Schneider Electric. He is active in Santa Clara Valley IEEE and is an IEEE Senior Member.


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